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Tutorial: Soldering Flip Chip and BGA Packages
Chip Scale Review Magazine The selection of solder, always an important issue, is particularly critical with flip chip and other miniature leadless packages, where the solder plays an increased structural role. Article by Mike Fenner, Indium Corp. Europe, London 
Introduction to Flip-Chip techniques part#1 IVF (The Swedish Institute of Production Engineering Research) Extensive introduction to flip-chip technology, with focus on materials, bonding techniques, reliability and design This is a part of the Nordic Electronics Packaging Guideline by The Swedish Institute of Production Engineering Research (IVF).
White Papers and Technical Reports Universal Instruments A collection of technical papers to help you keep up with this ever-evolving industry. They cover the following topics: Flip Chip and Die Placement Chip Scale Package (CSP) Circuit Board Technology Optoelectronics Pin-in-Paste 0201 Electrostatic Discharge (ESD) Adhesives and Dispensing Business and Operations
Introduction to Flip-Chip techniques part#2 IVF (The Swedish Institute of Production Engineering Research) Part#2 of IVF's Introduction to flip-chip techiques
Assembling Chip-Scale Packages with High Yields Requires Care with Printing and Reflow Processes Chip Scale Review Magazine Indium Coropration's advices on assembly of Chip Scale Packages, with a focus on solder paste printing and reflow soldering (added on 29-Dec-2002)
Wire Bonding IVF (The Swedish Institute of Production Engineering Research) Extensive introduction to wire-bonding technology, equipment, reliability and materials. This is a part of the Nordic Electronics Packaging Guideline by The Swedish Institute of Production Engineering Research (IVF).
The influence of PCB parameters on CSP assembly and reliability Advanced Packaging Extensive discussion about assembly and reliability of chip scale packages, and how these are affected by bare board parameters. (added on 17-May-2003)
Chip-Scale Package Assembly Reliability Chip Scale Review Magazine Although the weakest link of CSP assembly reliability is often internal package failure, solder-joint fatigue is still considered the key reliability factor.
The Latest in Underfill for Advanced Chip Assembly Circuits Assembly This file described investigations on a new dispenseless underfill process for CSP's, compatible with standard SMT-processing (added on 20-Sep-2003)
Solder Ball Endurance Advanced Packaging Article about the mechanical reliability of ball grid arrays and chip scale package device families, discussing solder voiding and material properties. (added on 15-Sep-2003)
Equipment Considerations for Flip-Chip Packaging Chip Scale Review Magazine As flip-chip-in-package (FCIP) continues to grow in popularity, the semiconductor packaging industry is acquiring a body of practical knowledge about factors related to cost, productivity and reliability. This summary covers some of the experience that Amkor has accumulated
Chip Scale Review Magazine Chip Scale Review Magazine
MANUFACTURING ROBUSTNESS OF CSP ON AN SMT LINE NASA Electronic Parts and Packaging Program This reports describes the tests that were done by Celestica to integrate CSPs into main stream surface mount technology (SMT) assembly. In this paper, the assembly process flow, solder paste for different stencil design, manufacturing defects, X-ray inspection results, and ultrasonic characterizations are reported. (added on 30-Apr-2003)
Introduction to CSP Technology IVF (The Swedish Institute of Production Engineering Research) Part#2 of IVF's introduction to Chip Scale Packaging Technology
Introduction to CSP Technology IVF (The Swedish Institute of Production Engineering Research) Good introduction to Chip Scale Packaging Technology by IVF (The Nordic Electronics Packaging Guideline)
Wafer-Level Ultra-Chip-Scale Package
Assembly Processes for Flip Chips on Substrates Advanced Packaging Study demonstrating the feasability of flip chip assembly on FR4 with and without nitrogen reflow. (added on 15-Nov-2003)
3-D Measurement System for Use in Microelectronics Advanced Packaging A study of the relationship between warp of BGA's and solder joint reliability, demonstrating a method to measure warping. (added on 15-Nov-2003)
Soldermask Registration Considerations for Fine-Pitch Area Array Package Assembly SMT Magazine This articles explains how solder mask registration can cause shorts when soldering fine-pitch BGA's or CSP's, and it provides some tips on how to avoid such problems. I believe it's just about a week ago that I experienced exactly this same problem, so you'd better read this article before it happens to you ! (added on 31-Mar-2004)
A Review and Trends in Flip-Chip Technology Chip Scale Review Although decades-old, flip-chip technology has only recently entered the packaging mainstream. This article presents an overview of different bumping technologies and reviews recent technology advances. (added on 11-Apr-2004)
Improving the Acceptance of Flip Chip Circuits Assembly Integrating flip chip attach (FCA) technology into surfacemount assembly lines has not been easy. Changes have to be made to the existing process, and new equipment has to be added. And not all FCA processes lend themselves to automated, in-line processing. (added on 11-Apr-2004)
Underfill Effects on BGA Drop, Bend, and Thermal Cycle Tests Advanced Packaging The use of a properly designed underfill can significantly improve drop and bend tests, and the thermal cycle performance of BGAs. (added on 06-Mar-2005)
BGA LAND PATTERN and ASSEMBLY Issues PCD&M Magazine While saving plenty in board real estate, BGAs and chip-scale packages carry a host of other considerations, from coplanarity to rework to reliability. (added on 07-Feb-2004)
Processing and Reliability of Corner-bonded CSPs Advanced Packaging This article presents an alternative to fully underfilling components to protect them from vibration, shock and dropping trauma. (added on 21-Mar-2004)
Assembly and Reliability of a Wafer-Level CSP Circuits Assembly An experiment reveals that wafer-level devices can be assembled in high yield using standard surface-mount practices. (added on 23-May-2004)
Assembly and Cleaning of CSPs for High, Low, and UltraLow Volume Applications. Nasa This paper presents lessons learned on assemblies with CSP's at three facilities with high, low, and ultralow volume production of. (added on 05-Aug-2004)
Troubleshooting Underfill Void Elimination Advanced Packaging This article explores strategies for troubleshooting void problems in underfills. (added on 18-Sep-2005)
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© 2004 Daan Terstegge - All rights reserved. |